This is part of an ongoing personal project that started in 2022. This hardware circuit is only designed to operate with signals between 0V to 5V.
The hardware for the digital oscilloscope is relatively
simple; the primary components are the GW1N-1 FPGA and the TLC0820AC flash ADC. The other sections of the hardware design are to
complement the ADC, specifically the low-pass filter to remove high frequency noise that is greater than 392kHz (maximum sampling frequency) and the buffer to prevent loading the portion of
a signal that is probed. Additionally, the buffer also clips the output if exceeds a certain limit to prevent damaging the ADC; in a following revision,
a clipping circuit is required, such as with Zener diodes.
The BNC connector with the input impedance circuit is designed similar to what is expected in a traditional oscilloscope input to operate
with conventional oscilloscope probes. Hence, this allows the digital oscilloscope to operate when the probe is configured for either X10 and X1 attentuation.
